This invention relates to an asynchronous static memory which consumes a small amount of power and can yet operate at a high speed even when the cycle time is long.
Static memories are classified into two types. The first type is a synchronous memory which is controlled by a sync signal supplied from an external device. The second type is an asynchronous memory which is not controlled by any sync signals.
A synchronous static memory consumes a small amount of power, but needs a sync signal (e.g., a chip-selecting signal or a chip-enabling signal) synchronous with an address change.
On the other hand, the asynchronous static memory does not need such a signal. However, it consumes much power since it includes a circuit in which a penetrating DC current flows between two power sources all the time the memory operates. A static memory of this type is disclosed in Osamu Minato, et al., "A HI CMOSII 8k.times.8b Static RAM" in Digest of Technical Papers, 1982, IEEE, International Solid-state Circuit Conference (ISSCC), pp. 256-257. Due to the penetrating current, it consumes much power regardless of its cycle time for data-writing or data-reading.
A new type of a static memory, called an "externally asynchronous, internally synchronous memory," has been developed. This memory is controlled by a sync signal generated within it. It is easy to operate and consumes a small amount of power. A static memory of this type is disclosed in Satoshi Konishi, et al., "A 64 Kb CMOS RAM" in Digest of Technical Papers, 1982, IEEE, International Solid-state Circuit Conference (ISSCC), pp. 258-259. In this synchronous memory, a change of an address is detected and a pair of bit lines is precharged within a period far shorter than the cycle time of the memory. At the same time, the bit lines are set to the same potential. Thereafter, a word line is energized to transfer data from a memory cell to the bit lines. A latch type sense amplifier then amplifies the the voltage between the bit lines, whereby the data is read through these lines. The amplifier consumes little power once it has latched the data, and helps to save power. It is necessary to amplify the voltage up to the power supply voltage. Hence, the bit lines cannot be quickly restored to the initial state in preparation for the next precharge. Therefore, the memory cannot operate at a high speed.